Download e-book for kindle: Analog Circuit Design: Low Voltage Low Power; Short Range by Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto

By Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto

ISBN-10: 9400719256

ISBN-13: 9789400719255

Analog Circuit layout comprises the contribution of 18 tutorials of the twentieth workshop on Advances in Analog Circuit layout. every one half discusses a particular to-date subject on new and important layout principles within the region of analog circuit layout. every one half is gifted through six specialists in that box and state-of-the-art info is shared and overviewed. This publication is quantity 20 during this profitable sequence of Analog Circuit layout, delivering beneficial details and perfect overviews of:

Topic 1 : Low Voltage Low energy, chairman: Andrea Baschirotto
Topic 2 : brief diversity instant Front-Ends, chairman: Arthur van Roermund
Topic three : strength administration and DC-DC, chairman : Michiel Steyaert.
Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the educational insurance additionally makes it compatible to be used in a sophisticated layout path.

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Extra resources for Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC

Example text

S. Kawahito, Low-power design of pipeline A/D converters, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2006, pp. 505–512 21. -C. Huang, T,-C. 5 mW pipelined ADC with a time sharing technique, in ISSCC Digest of Technical Papers, San Francisco, CA, USA, Feb 2010, pp. 300–301 22. P. 13um CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Dec 2006, pp. 832–841 23. M. 9b ENOB 40MS/s pipelined SAR ADC in 65 nm CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2010, pp.

Iroaga, B. Murmann, A 12-Bit 75-MS/s pipelined ADC using incomplete settling. IEEE J. Solid-State Circuits 42(4), 748–756 (2007) 69. S. , A 15b power-efficient pipeline A/D converter using non-slewing closedloop amplifiers, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2008, pp. 117–120 70. T. , Power dissipation bounds for high-speed Nyquist analog-to-digital converters. IEEE Trans. Circuits Syst. I 56(3), 509–518 (2009) Chapter 3 Low-Power Successive Approximation ADCS for Wireless Applications Jan Craninckx Abstract This chapter discusses the advancements made in SAR ADCs for wireless applications, which require accuracies in the range of 8–10 bit and a few 10’s of MHz sampling speed.

K. Gulati, Lee Hae-Seung, A low-power reconfigurable analog-to-digital converter. IEEE J. Solid-State Circuits 36(12), 1900–1911 (2001) 32. C. 5 V 12 b 5 MSample/s pipelined CMOS ADC, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 1996, pp. 314–315 33. D. , 55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. IEEE J. SolidState Circuits 41(7), 1589–1595 (2006) 34. S. 7 dB SNR CMOS pipeline ADC. IEEE J. Solid-State Circuits 44(12), 3305–3313 (2009) 35. -R. Kim, B. 95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration, in Proceedings of the ESSCIRC, Sevilla, Sept 2010, pp.

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Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC by Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto


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